Semiconductor memory devices comprise arrays of memory cells that are arranged in rows and columns. The gate electrodes of rows of memory cell transistors are connected by word lines, by which the memory cells are addressed. The word lines are shaped as word line stacks, which are arranged in parallel. The word lines are electrically insulated from one another laterally by dielectric material. Each word line is provided with a contact area at an end of the word line in a peripheral area. The contact areas have a larger lateral dimension than the striplike word line stacks. Therefore, the contact areas are arranged in a staggered fashion.
The lateral distance between two word line stacks and the width of the word line stacks sum to the pitch of the array of word lines. The pitch is the dimension of the periodicity of a periodic pattern or arrangement. The word line stacks succeed one another in a completely periodic fashion, in order to reduce the necessary device area as much as possible. If the word line array is structured by a usual photolithography technique, the lateral dimensions of the word line stacks and the width of the intermediate spaces can only be produced with the minimal value that is enabled by the applied photolithography, and the minimal possible pitch of the word line array is limited.